1. Field of the Invention
The present invention relates to a semiconductor memory device for temporarily storing digital image data.
2. Description of the Related Art
In recent years, there has been an increasing demand for systems capable of processing digital image data of high image quality at a high speed along with the development of multimedia computers and the digitization of TV systems. In order to process digital image data at a high speed, it is required to increase the access speed in a semiconductor memory device for temporarily storing digital image data, as well as to use a high-speed and high-performance processing apparatus.
Image data is mostly subjected to operation processing utilizing two-dimensional spatial dependence (correlation) of an image. For example, according to MPEG (Moving Picture Experts Group), image data is compressed and encoded by being subjected to DCT (Discrete Cosine Transform) processing on a rectangular region of 8.times.8 pixels basis. According to a multi-window system, rectangular regions of various sizes in a window displayed on a screen are required to be filled in with a background color at the time of an initial display of individual windows or clearing them. More specifically, according to these processings, image data in a rectangular region is successively and continuously accessed, so that access speed (in a row direction as well as in a column direction) of image data is required to be increased.
FIG. 12 shows a structure of a conventional DRAM (dynamic random access memory) which is mostly used as a semiconductor memory device for storing image data. The DRAM is supplied with an address Addr, a row address strobe signal RASbar, and a column address strobe signal CASbar from outside, whereby data DQ is input/output between the DRAM and the outside. The address Addr is sent to a row address latch 1 and a column address latch 2. The row address strobe signal RASbar and the column address strobe signal CASbar are sent to a clock generator 3. Based on these control signals, the clock generator 3 generates a row decode control signal RA, a column decode control signal CA, and a sense amplifier driving signal SA. The row address latch 1 receives the row decode control signal RA, latches a row address R, and sends it to a row decoder 21. The column address latch 2 receives the column decode control signal CA, latches a column address C, and sends it to a column decoder 5.
The row decoder 21 decodes the row address R, activates any word line WL.sub.(R) of a memory cell array 6, and selects a memory row. The memory cell array 6 is connected to a sense amplifier 6a and a column selector 6b. The sense amplifier 6a amplifies each data which is read onto bit lines from memory cells on a memory column basis. The sense amplifier 6a is driven when the sense amplifier driving signal SA becomes active. The column selector 6b selects a memory column of the memory cell array 6 in accordance with an output from the column decoder 5, and connects bit lines of the memory column to a data line DIO. The column decoder 5 decodes the column address C and sends the result of the decoding to the column selector 6b. The column selector 6b is connected to an input/output buffer 22 through one data line DIO. The input/output buffer 22 is a bidirectional three-state buffer for connecting the data line DIO to an external data bus or the like. Thus, the input/output buffer 22 allows data to be input/output between the DRAM and the outside.
The internal structure of the memory cell array 6 will be described with reference to FIG. 13. The memory cell array 6 includes a number of memory cells MC for storing data arranged in a matrix. The memory cell array 6 also includes a number of word lines WL, bit lines BL, and complementary bit lines BLbar in the row and column directions. A number of memory cells MC in the identical row (memory row) are connected to each word line WL. A number of memory cells MC in the identical column (memory column) are connected to each bit line BL and each complementary bit line BLbar. It should be noted that the memory cells MC in the identical column are alternately connected to each bit line BL and each complementary bit line BLbar. The row decoder 21 is connected to a number of word lines WL. A number of bit lines BL and complementary bit lines BLbar are connected to the sense amplifier 6a. Therefore, when any word line WL is activated by the row decoder 21, data is read from all the memory cells MC connected to the activated word line WL to each bit line BL or each complementary bit line BLbar and amplified by the sense amplifier 6a. When the column selector 6b shown in FIG. 12 connects any bit line BL or any complementary bit line BLbar to the data line DIO, the data can be read outside, or data from outside can be written in the memory cell MC through the bit line BL or the complementary bit line BLbar.
The operation in which data in a rectangular region of image data is successively and continuously accessed by using the above-mentioned conventional DRAM will be described with reference to FIG. 14. This figure shows the case where the whole data in a rectangular region of 8.times.8 pixels with a pixel corresponding to the row address R and the column address C being an origin (upper left corner) is written in the DRAM.
Furthermore, a page mode write cycle in which an access speed in the column direction is increased is used for this access.
The row address R is input as the address Addr from outside to the DRAM on standby, whereby the row address strobe signal RASbar falls at a time t.sub.11. At this time, the clock generator 3 allows the row decode control signal RA and the sense amplifier driving signal SA to rise, and the row address latch 1 latches the row address R. The row decoder 21 decodes the row address R and allows the word line WL.sub.(R) of the memory cell array 6 to rise. Then, data from all the memory cells MC.sub.(R,O) through MC.sub.(R,W) in a selected memory row are read onto the bit lines BL or the complementary bit lines BLbar, and one row of data is amplified by the sense amplifier 6a driven by the rise of the sense amplifier driving signal SA. Next, the column address C is input as the address Addr to the DRAM, whereby the column address strobe signal CASbar falls at a time t.sub.12. At this time, the clock generator 3 allows the column decode control signal CA to rise, and the column address latch 2 latches the column address C. The column decoder 5 decodes the column address C and allows only a decode output YS.sub.(C) to rise. Then, in the memory cell array 6, one bit line BL and one complementary bit line BLbar in a memory column corresponding to the column address C are connected to the data line DIO through the column selector 6b, whereby data input from outside is written in a memory cell MC.sub.(R,C).
Once the above-mentioned write is completed, the column address strobe signal CASbar is allowed to rise. Then, the data line DIO is pre-charged by a control signal (not shown) to go to standby. Then, a column address C+1 is input as the address Addr to the DRAM, whereby the column address strobe signal CASbar falls at time t.sub.13. At this time, the column address latch 2 latches the column address C+1, and the column decoder 5 allows only a decode output YS.sub.(C+1) to rise. In the memory cell array 6, one bit line BL and one complementary bit line BLbar corresponding to the column address C+1 in the same memory row as the above are connected to the data line DIO through the column selector 6b, whereby data input from outside is written in a memory cell MC.sub.(R,C+1) through one bit line BL and one complementary bit line BLbar. Thereafter, the column address strobe signal CASbar is allowed to fall while the column address C is successively increased in the same way as the above. Thus, data from outside is written in memory cells MC.sub.(R,C+2) through MC.sub.(R,C+6) in a plurality of memory columns in the same memory row as the above of the memory cell array 6.
Finally, a column address C+7 is input as the address Addr to the DRAM, whereby the column address strobe signal CASbar falls at time t.sub.14. At this time, the column decoder 5 allows only a decode output YS.sub.(C+7) to rise. In the memory cell array 6, data from outside is written in a memory cell MC.sub.(R, C+7) in a memory column corresponding to the column address C+7 in the same memory row as the above. Then, the column address strobe signal CASbar and the row address strobe signal RASbar are allowed to rise at time t.sub.15, whereby the DRAM is returned to standby. When the row address strobe signal RASbar rises, all the bit lines BL and the complementary bit lines BLbar are pre-charged.
The row address R input as the address Addr is updated to a row address R+1, whereby the row address strobe signal RASbar falls at time t.sub.16. At this time, the row decoder 21 decodes the row address R+1 and allows a word line WL.sub.(R+1) in the memory cell array 6 to rise. In the memory cell array 6, data is read onto the bit lines BL or the complementary bit lines BLbar from all the memory cells MC(R+1,0) through MC(R+1,N) in a selected memory row and amplified by the sense amplifier 6a.
Next, the column address C is input as the address Addr to the DRAM, whereby the column address strobe signal CASbar falls at time t.sub.17. At this time, the column decoder 5 decodes the column address C and allows only the decode output YS.sub.(C) to rise. In the memory cell array 6, data input from outside is written in a memory cell MC.sub.(R+1,C).
Once the above-mentioned write is completed, the column address strobe signal CASbar is allowed to rise. Then, the row address C+1 is input as the address Addr to the DRAM, whereby the column address strobe signal CASbar falls at time t.sub.18. At this time, the column decoder 5 allows only the decode output YS.sub.(C+1) to rise. In the memory cell array 6, data input from outside is written in a memory cell MC.sub.(R+1,C+1). Then, the column address strobe signal CASbar is allowed to fall while the column address C is successively increased in the same way as the above. Thus, data from outside is written in the remaining memory cells MC.sub.(R+1,C+2) through MC.sub.(R+1,C+7) in the same memory row as the above of the memory cell array 6. Then, the column address strobe signal CASbar and the row address strobe signal RASbar are allowed to rise at time t.sub.19, whereby the DRAM is returned to standby.
Furthermore, when the similar operation is repeated while the row address R is successively increased, data is successively written from outside to 8 memory cells MC in each row. When data is written from outside to the last memory cell MC.sub.(R+7,C+7) at time t.sub.20, the column address strobe signal CASbar and the row address strobe signal RASbar are allowed to rise at time t.sub.21, whereby the access to the rectangular region is completed.
In the above-mentioned conventional DRAM, the column address strobe signal CA is repeatedly allowed to fall in accordance with a page mode, whereby the memory cells in the identical column can be accessed at a high speed. However, in the case where the memory cells MC in a different row are accessed, it is required to return the DRAM to standby by once allowing the address strobe signal RASbar to rise. Thus, the access speed in the row direction is lower than that in the column direction. More specifically, a period of time for the row decoder 21 to inactivate the word line WL and to disconnect the memory cells MC from the bit lines BL or the complementary bit lines BLbar, a period of time for pre-charging these bit lines BL or complementary bit lines BLbar, a period of time for inputting a new row address R and for the row decoder 21 to activate another word line WL, and a period of time for the sense amplifier 6a to amplify data read from the memory cells MC in the new memory row to each bit line BL and complementary bit line BLbar are required before the subsequent access.
Therefore, in spite of the fact that the frequency of access to image data in a relatively small rectangular region is high in encoding and decoding processing according to the MPEG, the multi-window system, and the like, the conventional DRAM for temporarily storing image data has the disadvantage of preventing a system from processing image data at a high speed due to slow access in the row direction.